|
課程名稱 |
半導體電子產品工程
Semiconductor Electronic Product Engineering |
|
開課學期 |
107-2 |
|
授課對象 |
電機資訊學院 電子工程學研究所 |
|
授課教師 |
潘正聖 |
|
課號 |
EEE5054 |
|
課程識別碼 |
943 U0560 |
|
班次 |
|
|
學分 |
3.0 |
|
全/半年 |
半年 |
|
必/選修 |
選修 |
|
上課時間 |
星期三6,7,8(13:20~16:20) |
|
上課地點 |
電二141 |
|
備註 |
總人數上限：12人 |
|
Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1072EEE5054_ |
|
課程簡介影片 |
|
|
核心能力關聯 |
核心能力與課程規劃關聯圖 |
|
課程大綱
|
|
為確保您我的權利,請尊重智慧財產權及不得非法影印
|
|
課程概述 |
Semiconductor electronics product engineering techniques, covering knowledge in process, device, circuit design, test, Q/R etc., as well as the teamwork among domain specialists to drive for product success. |
|
課程目標 |
. |
|
課程要求 |
|
|
預期每週課後學習時數 |
|
|
Office Hours |
另約時間 備註： 請學生先和老師聯絡，並確定時間/地點。 |
|
指定閱讀 |
Digital Integrated Circuits: A Design Perspective, 2nd edition by Jan M. Rabaey (教科書) |
|
參考書目 |
1. VLSI Technology, 2nd edition by S. Sze
2. Physics of Semiconductor Devices, 2nd edition by S. Sze
3. VLSI Test Principles and Architectures, edited by LT Wang, CW Wu and XQ Wen,
2006 *
4. System on Chip Test Architectures, edited by LT Wang, CE Stroud and NA
Touba, 2008 *
5. Applied Reliability, 3rd edition by P. Tobias
6. Reliability Physics and Engineering, 2nd edition by J. W. McPerson
7. Intel Quality Handbook, 2014 *
8. Renesas Semiconductor Reliability Handbook, 2017 *
* Some material in these references as well as the lecturer's past experiences
will be covered |
|
評量方式
(僅供參考) |
|
No. |
項目 |
百分比 |
說明 |
|
1. |
期中考口試 |
50% |
Open-book 個別口試，學生主動向老師提出 考試時間 (約一小時) |
2. |
期末口頭暨書面報告 |
50% |
相關時間表將於期中考後再公布。 |
|
|
週次 |
日期 |
單元主題 |
|
第1週 |
2/20 |
Semiconductor electronics product engineering overview, Ch 1 |
|
第2週 |
2/27 |
Overview of process/device technology, Ch 2-3 |
|
第3週 |
3/06 |
Q&R fundamentals and process/product qualification fundamentals, HBs |
|
第4週 |
3/13 |
Wires; CMOS inverters, Ch 4-5 |
|
第5週 |
3/20 |
停課 |
|
第6週 |
3/27 |
Combinational logic, Ch 6 |
|
第7週 |
4/03 |
春假 |
|
第8週 |
4/10 |
Sequential logic, Ch 7 |
|
第9週 |
4/17 |
Midterm oral exam (1-1) |
|
第10週 |
4/24 |
Product implementation strategies; interconnect , Ch 8-9 |
|
第11週 |
5/01 |
Timing issues, Ch 10 |
|
第12週 |
5/08 |
Datapath structures, Ch 11 |
|
第13週 |
5/15 |
Memory/Array structures, Ch 12 |
|
第14週 |
5/22 |
Design for test fundamentals, VLSI Ch 2 |
|
第15週 |
5/29 |
Automatic test pattern generation fundamentals, VLSI Ch 4 |
|
第16週 |
6/05 |
Product failure diagnosis fundamentals, VLSI Ch 7 |
|
第17週 |
6/12 |
Product debug fundamentals, SOC Ch 10 |
|
第18週 |
6/19 |
Final presentation/written project due |
|